Xilinx / Xilinx/Vitis-Tutorials
can't compile for tutorial VC1902 (Could not load Device Part .. )
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Description
Hi, this is the summary of my problem.
Environment:
- Vitis/Vivado 2026.1
- Ubuntu 22.04
- Vitis-Tutorials branch: 2026.1
- Tutorial:
Getting_Started/Vitis/Versal_w_PetaLinux/VCK190
Command:
make all
Error:
INFO: [aiecompiler 77-749] Reading logical device VC1902
AIEbuild feature license is found.
INFO: [aiecompiler 77-750] Reading physical device xcvc1902-vsva2197-2MP-e-S
ERROR: [aiecompiler 77-6572] Could not load Device Part xcvc1902-vsva2197-2MP-e-S
Vivado Tcl also cannot find the part:
Vivado% get_parts vc1902
WARNING: [Coretcl 2-179] No part matched the expression you provided ("vc1902").
RDI_DATADIR inside Vivado:
RDI_DATADIR =
/tools/Xilinx/2026.1/SharedData/data:/tools/Xilinx/2026.1/data
The device file exists:
/tools/Xilinx/2026.1/data/devices/VC1902.json
Versal AI Core Series and Engineering Sample device support
are installed.
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First steps
- Read the whole issue, then the project's contributing guide.
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- Open a pull request that references the issue number.
Research direction
Start in Getting_Started/Vitis/Versal_w_PetaLinux/VCK190 and reproduce the issue with make all. Check the reported Vivado get_parts *vc1902* result alongside the RDI_DATADIR and VC1902.json paths; done means the tutorial can locate the device part and compile successfully.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- ubuntu
- Domain
- build-system, devtools, embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Active
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100