Xilinx / Xilinx/Vitis-Tutorials
01-rtl_kernel_workflow Running indefinitely on Alveo U280
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- Dominant language
- C
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Description
Hey, I am facing an issue with the feature tutorial for the rtl-kernel-workflow. I'm working with the Alveo U280 and the host code and rtl kernel are all packaged, compiled, and built successfully in vivado and vitis. The problem happens when running the built project in Hardware Emulation where its starts but the read loop just goes on indefinitely. I suspect it's something to do with the memory addresses and I checked that the host code had the same offsets with the ones assigned during packaging. I'm using Vitis and Vivado 2022.1 if that helps, and I used the same branch version of the tutorial along with the latest version too but both have the same results.
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Research direction
Start with the 01-rtl_kernel_workflow feature tutorial and reproduce the read loop in Hardware Emulation using the reported Alveo U280, Vitis, and Vivado 2022.1 setup. Compare the host offsets with the packaging assignments, then document the cause and verify that the loop terminates successfully.
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Assessment
- Tech stack
- c
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100