Xilinx / Xilinx/Vitis-HLS-Introductory-Examples

RTL blackbox flow

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Dominant language
ReScript
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Forks
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No merged PRs in 30d

Description

Misc/rtl_as_blackbox/
I follow this flow for simulation, and everything is good.
However, when I try to move it to HW, I get the following error
image
image

Can we have an end-to-end example of RTL black-box flow to deploy on HW? Or can anybody tell me how to solve it?

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First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start with Misc/rtl_as_blackbox/ and review the two attached error screenshots to identify where the simulation-to-hardware flow diverges. Document an end-to-end hardware deployment path for the RTL black-box example, or record the concrete resolution for the reported error; completion should be verifiable by deploying the example on hardware.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot
Issue type
Documentation
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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