Does the wasm memory model have tear-free non-atomic loads?

We recently learned that Musl (used in both wasi-libc and Emscripten) is using non-atomic 32-bit aligned loads from memory locations which can be stored to by other threads without synchronization, apparently on the assumption that compilers will always codegen these to a single instruction, effectively intending something like a very relaxed ordering. On Wasm, LLVM compiles these to plain i32.load wasm instructions.

Are there any guarantees in the proposed Wasm memory model that a plain aligned i32.load of memory that can be simultaneously stored to by aligned i32 stores in other threads won't tear?

Read the proposed Wasm memory model and the seven comments on this issue, starting with the question about plain aligned i32.load instructions and concurrent aligned i32 stores. Determine whether the proposal guarantees tear-free non-atomic loads, then document the conclusion or identify the specification change needed.