Vector35 / Vector35/binaryninja-api
RISC-V: CSR instruction disassembly: Decode CSR register number into a string when a standardized register is used
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- C++
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Description
Currently, CSR instructions are decoded like so:
But there are many CSR register numbers with a defined definition in the RISC-V ISA Manual Volume II: Privileged Architecture. Examples:
I propose instead of the disassembly showing csrrs zero, 0x300, t0, it instead show csrrs zero, mstatus, t0. Likewise in the higher-level ILs.
I can make these changes, but I'm not great at Rust and I need some pointers on how to do it. Providing an example of the aforementioned instruction would suffice and I could then fill in the rest.
Based on recent contributors, I will humbly ask @emesare, @ehntoo for assistance.
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
No file or test is named. Start by locating the RISC-V CSR instruction disassembly and higher-level IL entry points, then review how CSR register numbers are represented. Done means standardized CSR numbers such as 0x300 are rendered as names such as mstatus in both disassembly and the higher-level ILs.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp, rust
- Domain
- reverse-engineering
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100