Time-Appliances-Project / Time-Appliances-Project/Time-Card
Production Timecard: mismatch between board and FPGA PCIe lane counts
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Description
The production board schematic description on sht. 1 says "X4 PCIE TIME CARD", and four lanes are routed between the edge connector and FPGA (schematic and board). However, the production FPGA only uses a single lane. This lane is correctly attached to the TX0 and RX0 pairs in the board design.
It works, no doubt, but there may be missed expectations for new users.
If going to an x4 channel, during FPGA synthesis are the additional pairs guaranteed to go to the pins already connected on the board?
[ from Vivado block diagram ]
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by comparing the production board schematic description on sheet 1, the board routing, and the Vivado block diagram referenced in the issue. Determine whether the four routed PCIe lanes are intended to be usable by the production FPGA and document or correct the mismatch so the lane-count expectations and pin connections are unambiguous.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100