Time-Appliances-Project / Time-Appliances-Project/Time-Card
Production Timecard: bad termination on FPGA JTAG with USB
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Description
Ref. schematic R4006-G0001-03-SC-REV02.pdf
If using the USB interface (FT432, sht. 24), the FPGA JTAG signals are double-terminated by resistors shown at sht. 24, zone B11:
and sht. 10, zone J4.
by way of the mux'ing shown on sht. 24 "JTAG/SPI_MASTER_SEL".
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the referenced schematic R4006-G0001-03-SC-REV02.pdf, checking sheet 24 zone B11 and sheet 10 zone J4 around the FPGA JTAG signals and the JTAG/SPI_MASTER_SEL mux. Done means resolving the double termination for the USB interface in the production schematic and verifying the affected connections.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Clearly specified
- Newbie friendliness
- 35/100