`VerilogWriter::writeAssigns()` omitted `assign` statement when a feed-through net name matches output port name

VerilogWriter::writeAssigns(const Instance *inst) assumes that a feed-through net name should match its input port name.

• If a feed-through net name matches its input port name, assign statement is correctly generated when write_verilog command is exectued because the net name is different to its output port name.

Case 1.
(input term name:  IN)  -->  (feed-through wire name: IN)  --> (output term name: OUT)

[ Verilog output by write_verilog command ]

module sub (IN, OUT);
  input IN;
  output OUT;
  assign OUT = IN;             // Correct
endmodule

• But if a feed-through net name matches its output port name, assign statement is not generated.

Case 2.
(input term name:  IN)  -->  (feed-through wire name: OUT)  --> (output term name: OUT)

[ Verilog output by write_verilog command ]

module sub (IN, OUT);
  input IN;
  output OUT;
                         // ERROR. assign statement is missing
endmodule

It would be nice if VerilogWriter::writeAssigns() can generate the assign statement correctly even if the feed-through net name is the same as the output term name.