The-OpenROAD-Project / The-OpenROAD-Project/OpenSTA
How to model the capacitance of a VIA?
Nobody has claimed this yet.
- Dominant language
- Verilog
- Stars
- 619
- Forks
- 270
- Avg merge
- 5d 15h
- Merged PRs (30d)
- 4
Description
I found that only RESISTANCE is predefined in *.tlef file for a VIA. I am wondering how to extract the parastistic capacitance parameter for a VIA since I know OpenSTA is able to evaluate the post-routing timing performance.
Could u please give me some guidance and tell me which part of code is corresponding to?
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue names no source file, test, or entry point. Start by locating VIA handling and parasitic-capacitance extraction in OpenSTA, then determine how the existing post-routing timing flow obtains capacitance and what documentation or implementation would answer the question.
Written by the indexing model from the issue text.
Assessment
- Domain
- tooling
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100