OpenROAD doesn't write internal power connections ( multiple pins connected to same power rail ).

Describe the bug

In the chipfoundry openframe, you have several power pins ( different names ) all wired internally to the same power net ( that has a name not matching any of the port names ).

This is represented just fine in the internal DB and in the DEF export but when writing a verilog that connection is not represented.

Previously it would write assign statements and LVS would work just fine, but with recent OpenROAD nothing is written, breaking LVS checks.

Expected Behavior

It should write assign statements between port name and net name like it did before.

Environment

Above command doesnt work ...

I'm debugging using OpenROAD from git commit
4982f54961688294d6104e948395af3f3d7289e2

Problem also exists in the nix environment from LibreLane 3.0 release.

To Reproduce

rep.zip

openroad -db openframe_project_wrapper.odb
write_verilog -include_pwr_gnd test.v

Then observe how in test.v there is no connection between for instance vccd1 and vdpwr even though if you write a DEF you will see

- vccd1 + NET vdpwr + DIRECTION INPUT + USE POWER

showing that port is connected to that net.

Relevant log output

Screenshots

No response

Additional Context

No response