The-OpenROAD-Project / The-OpenROAD-Project/OpenROAD
ram: Verify that the decoder is fully hierarchical
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ram
- Dominant language
- Verilog
- Stars
- 3.1k
- Forks
- 1k
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 136
Description
Ensure that the ram decoder scales to arbitrary levels, beyond just a single level. This should be verified by scaling up the decoder to 2,3,4-deep levels of AND gates and checking both the logical function and physical placement of cells is working correctly.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Locate the RAM decoder and its current single-level verification first. Exercise 2-, 3-, and 4-level AND-gate hierarchies, checking both logical behavior and physical cell placement. The work is done when all requested depths pass both checks.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100