SpinalHDL / SpinalHDL/SpinalHDL
Provide some API to speed up SpinalSim hardware signal read
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- Dominant language
- Scala
- Stars
- 2k
- Forks
- 391
- Avg merge
- 1d 22h
- Merged PRs (30d)
- 5
Description
I just mesured the time needed to read a signal value using the verilator backend :
bt1.toLong => 40 ns
vs
manager.getLong(signal1) => 5 ns,
Redondant code avoided :
val manager = SimManagerContext.current.manager
val signal1 = manager.raw.userData.asInstanceOf[ArrayBuffer[Signal]](bt1.algoInt)
So, adding some API to provide a optimized signal access could realy help speeding up things for performance critical testbench
CPU used to test, AMD 5800X3D
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
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- Open a pull request that references the issue number.
Research direction
Start by tracing the Scala access paths shown—bt1.toLong, SimManagerContext.current.manager, and manager.getLong(signal1)—through the Verilator backend. Compare their overhead and benchmark any public API against the reported 40 ns versus 5 ns reads; done means an optimized signal-access API with measurable improvement for performance-critical testbenches.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- performance, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100