SciML / SciML/ModelingToolkitStandardLibrary.jl
How to model ADC/DAC
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- Dominant language
- Julia
- Stars
- 171
- Forks
- 49
- Avg merge
- 15h 50m
- Merged PRs (30d)
- 10
Description
Is it already possible to model ideal and non-ideal analog-digital-converters (ADC) or DACs given the parts in the standard library?
Thanks :)
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
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Research direction
The issue names no files, tests, or entry points. Inspect the standard library components to determine whether ideal and non-ideal ADC/DAC models can be assembled from existing parts; done means clearly reporting the available support or defining the missing modeling work.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- julia
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100