RT-Thread / RT-Thread/rt-thread
[Feature] riscv进行上下文切换的时候是否需要内存屏障fence指令呢？
Open
Nobody has claimed this yet.
Arch: RISC-V
enhancement
Kernel
- Dominant language
- C
- Stars
- 12.2k
- Forks
- 5.4k
- Avg merge
- 4d 12h
- Merged PRs (30d)
- 40
Description
Affected area
Kernel
Hardware/BSP vendor
Not applicable / Other
Architecture
RISC-V
Describe problem solved by the proposed feature
riscv进行上下文切换的时候是否需要内存屏障fence指令呢？
Describe your preferred solution
No response
Describe possible alternatives
No response
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue does not name files or tests. Start by locating the RISC-V kernel context-switch implementation and reviewing its memory-ordering assumptions; determine whether a fence is required and document or implement the agreed behavior, then validate it on the relevant RISC-V BSP.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c
- Domain
- embedded-iot, operating-systems
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100