[Bug] riscv interrupt could not be nested

RT-Thread Version

master

Hardware Type/Architectures

RISC-V with CLIC Interrupt

Develop Toolchain

GCC

Describe the bug

The interrupt handling logic for risc-v, see as below

https://github.com/RT-Thread/rt-thread/blob/fcd0b1e6797cbdca987f24d7c24a032709e5e53b/libcpu/risc-v/common/interrupt_gcc.S#L101-L109

In line 101, if another higher priority interrupt is nested(since in rt_hw_do_after_save_above, it will re-enable interrupt to allow higher priority interrupt), then it will switch from interrupt stack to task stack. I think if interrupt nesting is supported, it is better to nest in the interrupt stack to avoid corrupting the task stack.

Maybe here it should check whether interrupt is nesting or not to determine whether switch between interrupt stack and task stack.

Thanks

Other additional context

No response

Start with libcpu/risc-v/common/interrupt_gcc.S at lines 101-109 and trace rt_hw_do_after_save_above, focusing on how a higher-priority nested interrupt changes interrupt and task stack selection. Reproduce or reason through nested RISC-V CLIC interrupts with GCC, and consider the issue resolved when nesting no longer risks corrupting the task stack.