FlyDSL Development Roadmap (v0.3)

FlyDSL Development Roadmap (v0.3)

Modeled on the SGLang AMD roadmap (sgl-project/sglang#23494). Milestone: v0.3 · due 2026-07-05 · ▶ in progress.

Contributions and feedback are welcome.

FlyDSL (Flexible LaYout DSL) is the Python front-end of the project. Legend: ✓ done · ▶ in progress · ○ planned.

Focus

• Type system & IR: Closed DslType system and a coherent IR location policy for traced primitives.
• Robust AOT: Reliable ahead-of-time compilation.
• Frontier kernels: Flash Attention v3 and Mega MoE v1 with Expert Parallel.
• New hardware: Full gfx1250 support, validated end-to-end.

Feature and Performance Improvements (v0.3 in progress)

• Type system & IR
  PoC: @sjfeng1999
  Goal: Closed, coherent type and IR foundation for traced primitives.

  • ▶ Enforce DslType closure across expr primitives (DslType in → DslType out) #617
  • ▶ Define a coherent IR location policy for traced primitives #618
  • ▶ Support per-dimension layout-dynamic marking #619

• Robust AOT
  PoC: @coderfeli
  Goal: More robust ahead-of-time compilation.

  • ▶ More robust AOT #621

• Flash Attention v3
  PoC: @coderfeli
  Goal: FA v3 in FlyDSL.

  • ▶ Flash attention v3 #622

• Mega MoE v1 & Expert Parallel
  PoC: @XingerZhu @yanboshao
  Goal: First Mega MoE pipeline plus EP support.

  • ▶ Mega MoE v1: dispatch + gemm1, gemm2 + combine #626
  • ▶ FlyDSL EP support #628

• gfx1250 enablement
  PoC: @coderfeli
  Goal: Full gfx1250 support, validated end-to-end.

  • ▶ Full gfx1250 support and e2e validation #620
  • ○ Remove #ifdef dead-code guard on mgpuLaunchClusterKernel #380

Previous: v0.2 (released) · Next: v0.4. All milestones: https://github.com/ROCm/FlyDSL/milestones

Start by reviewing the v0.3 milestone and its linked child issues, especially #617–#628, to understand the work grouped under this roadmap. Completion is reflected by the roadmap statuses and the progress of those linked issues; this issue itself does not name a file, test, or standalone change.