Add support for SystemVerilog
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- Dominant language
- JavaScript
- Stars
- 13k
- Forks
- 1.4k
- Avg merge
- 15h 36m
- Merged PRs (30d)
- 3
Description
Language
SystemVerilog is the industry standard Hardware Description Language (HDL) used in the semiconductor industry for defining hardware designs and writing object-oriented code, constraint solvers, and assertions to verify those designs.
Prism currently only supports Verilog which is a much smaller subset of SystemVerilog.
Additional resources
SystemVerilog Wikipedia
SystemVerilog Language Reference Manual
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading Prism's existing Verilog support and the linked SystemVerilog Language Reference Manual. Determine the SystemVerilog syntax that must be covered and how Prism language definitions are structured; done means Prism highlights SystemVerilog code correctly across the required constructs.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- javascript
- Domain
- tooling
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100