Provide an option to reset persisting-L2 state between benchmark cells
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- Dominant language
- Cuda
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Description
Problem
Benchmarks that enable a CUDA persisting-L2 access policy can leave process-wide state behind for later NVBench benchmark cells. In particular, cudaLimitPersistingL2CacheSize and persisting cache lines can survive after the benchmark that configured them. A later benchmark in the same process can then measure a different cache configuration than it requested.
CCCL's DeviceHistogram benchmark work initially handled this by repeating the following before every measured launch:
cudaDeviceSetLimit(cudaLimitPersistingL2CacheSize, 0);
cudaCtxResetPersistingL2Cache();
That is easy for individual benchmarks to forget and requires the custom timer API to keep the reset outside the timed region.
Proposed behavior
NVBench should provide a benchmark option that restores the default persisting-L2 reservation and demotes persisting lines before a measured launch. This could be enabled by default with an opt-out, or exposed as an explicit state/benchmark option.
The reset should happen outside the measured interval and should report CUDA failures rather than silently continuing.
Motivation
Centralizing this in NVBench prevents one benchmark from contaminating later cells and avoids copying the same setup into every affected benchmark. This came up during review of NVIDIA/cccl#10555.
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- Read the whole issue, then the project's contributing guide.
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Research direction
Start by tracing NVBench's benchmark-option and custom-timer paths to find where setup occurs relative to a measured launch. Verify that the persisting-L2 reset runs outside the timed interval and that CUDA failures are reported; done means later benchmark cells no longer inherit the prior persisting-L2 state.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- performance
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 55/100