NVIDIA / NVIDIA/cutlass

[QST] Question about UniversalFMA

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Description

What is your question?

When executing the sgemm_70.cu program, I used the print_latex tool to observe the structure of mmaC, and its specific details are shown in the figure.

Image

As far as I know, UniversalFMA uses CUDA Cores for computation. However, during the execution of the General Matrix Multiplication (GEMM) operation, a puzzling phenomenon occurred: it seems that a thread can access the values in the internal registers of other threads. For example, thread T17 can read the values in the registers of threads T1 and T16 to complete the computation.
I'm wondering if you could kindly explain to me the reason behind this behavior?

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Research direction

Start by running sgemm_70.cu and reviewing the print_latex output for mmaC, then trace the UniversalFMA behavior in the relevant CUTLASS examples or documentation. Done means providing a clear explanation of how the observed values from threads T1 and T16 relate to T17's computation.

Written by the indexing model from the issue text.

Assessment

Tech stack
cpp
Domain
hpc
Issue type
Documentation
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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