[ENHANCEMENT]: Enable `packed_cas` codepath using 16B CAS on sm_90+ architectures
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Description
Is your feature request related to a problem? Please describe.
The packed_cas update routine shows better performance compared to back_to_back_cas and cas_dependent_write.
On sm_90 and higher we have hardware support for 16B atomic CAS which we currently don't make use of.
Describe the solution you'd like
16B atomicCAS was introduced with CUDA 12.3 (see docs).
Idea: Add a dedicated codepath for sm_90+ by adding something like
NV_IF_TARGET(some_target_that_means_sm_90_or_higher,
atomicCAS(...) // 16B CAS,
// pre-sm_90 code path);
Describe alternatives you've considered
Convince CCCL to expose cuda::atomic_ref::compare_exchange_* for 16B types ;)
Additional context
No response
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the packed_cas update routine and compare it with the back_to_back_cas and cas_dependent_write paths. Check the CUDA 12.3 atomicCAS documentation and the existing target-selection mechanism, then verify that sm_90+ uses 16B CAS while earlier architectures retain their current path.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- performance
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100