[FEA]: Enable transaction accounting on all barriers

### Is this a duplicate?

- [X] I confirmed there appear to be no [duplicate issues](https://github.com/NVIDIA/cccl/issues) for this request and that I agree to the [Code of Conduct](CODE_OF_CONDUCT.md)

### Area

libcu++

### Is your feature request related to a problem? Please describe.

Reported by @griwes and @miscco in [this thread](https://github.com/NVIDIA/cccl/pull/358#issuecomment-1684241960). Quoting @griwes:

> I am not convinced about only supporting this on sm_90+ and on shmem barriers. For a future memcpy_async_tx, we'll just do a fallback and never issue tx-based instructions for those cases, so if arrive_tx is just an arrive there (essentially discarding the tx count), that should be fine, no?
>
> I'd like our users to be able to just write the same code everywhere, have it use hardware features where available, and do a fallback everywhere else where possible (so only trap for cases where we can't tell what the correct thing to do is, like in the barrier in cluster shmem case).

cc @ahendriksen

### Describe the solution you'd like

See above.

### Describe alternatives you've considered

_No response_

### Additional context

_No response_

The issue identifies libcu++ and points to the discussion in PR #358, but it names no files, tests, or entry points. Start by reading the linked discussion and locating the libcu++ barrier implementation and its existing transaction-accounting coverage. Done means the intended behavior for all barrier cases is agreed and implemented with corresponding validation.

Written by the indexing model from the issue text.