NVIDIA / NVIDIA/cccl

[FEA]: Add atomic segmented sort kernel specialization

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Description

### Is this a duplicate?

- [x] I confirmed there appear to be no [duplicate issues](https://github.com/NVIDIA/cccl/issues) for this request and that I agree to the [Code of Conduct](CODE_OF_CONDUCT.md)

### Area

CUB

### Is your feature request related to a problem? Please describe.

The fused prefix-sort-and-bin producer can finish tiny segments, but there is no path that consumes its remaining work with CUB primitives.

### Describe the solution you would like

Add an internal atomic segmented-sort specialization that:

- Runs the fused producer, which fully sorts segments of length ≤32 and atomically bins the rest.
- Dispatches remaining bins to CUB: `WarpMergeSort` (64–256), `BlockMergeSort` (512–8192), and `DeviceSegmentedRadixSort` (larger segments).
- Ensures each segment is completed exactly once, either by the producer or its CUB bin.

Include correctness coverage at bin boundaries and benchmarks against the LRB path.

Close when this composed path is tested, and benchmarked.

### Describe alternatives you have considered

_No response_

### Additional context

- Building blocks: #10792 and #10804
- LRB kernel tracking: #10946

Contributor guide

Open the contributing guide

Research direction

Start with building blocks #10792 and #10804, then read the LRB kernel tracking in #10946. Trace the fused prefix-sort-and-bin producer and its CUB paths for the stated segment-size ranges. Done means the composed path completes every segment exactly once, has correctness coverage at bin boundaries, and is benchmarked against the LRB path.

Written by the indexing model from the issue text.

Assessment

Tech stack
cpp
Domain
hpc, performance
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Active
Clarity
Mostly clear
Newbie friendliness
35/100

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