[FEA]: Add runtime orchestration for graph-capturable segmented sort

### Is this a duplicate?

- [x] I confirmed there appear to be no [duplicate issues](https://github.com/NVIDIA/cccl/issues) for this request and that I agree to the [Code of Conduct](CODE_OF_CONDUCT.md)

### Area

CUB

### Is your feature request related to a problem? Please describe.

The segmented-sort work plan is produced on the device, but sizing subsequent kernel grids from exact device counts requires a device-to-host copy and stream synchronization. This prevents CUDA graph capture and adds a host round trip in the middle of the algorithm.

### Describe the solution you'd like

Track the runtime-orchestration work needed to launch the specialized segmented-sort kernels without a host synchronization step:

- [ ] SM-scaled fixed-grid scheduling whose work bounds remain device-resident.
- [ ] PDL evaluation for overlapping independent specialized kernel families.

This tracking issue can be closed once the specialized kernel sequence can consume device-resident work plans without a mid-algorithm host synchronization and has appropriate graph-capture correctness coverage.

### Describe alternatives you've considered

_No response_

### Additional context

- Existing PDL issue: https://github.com/NVIDIA/cccl/issues/6790
- Existing graph-capture design/PoC/evaluation issues: https://github.com/NVIDIA/cccl/issues/10798, https://github.com/NVIDIA/cccl/issues/10799, and https://github.com/NVIDIA/cccl/issues/10800

Start by reading the linked PDL issue 6790 and the graph-capture design, proof-of-concept, and evaluation issues 10798–10800. Determine how segmented-sort's device-produced work plan is consumed and how the specialized kernel sequence can avoid host synchronization. Done means device-resident work plans support graph capture with correctness coverage, including SM-scaled scheduling and PDL evaluation.

Written by the indexing model from the issue text.