[FEA]: Optimize the runtime-width group merge-sort primitive for segmented sort

### Is this a duplicate?

- [x] I confirmed there appear to be no [duplicate issues](https://github.com/NVIDIA/cccl/issues) for this request and that I agree to the [Code of Conduct](CODE_OF_CONDUCT.md)

### Area

CUB

### Is your feature request related to a problem? Please describe.

The initial runtime-width group merge-sort primitive can provide the required cooperative sorting behavior for sub-warp, warp, and multi-warp groups without incorporating every performance optimization. Independent techniques may improve register pressure, memory efficiency, or avoid redundant work, but should be evaluated against a correct baseline.

### Describe the solution you'd like

Evaluate and, where beneficial, integrate the following optimizations into the runtime-width group merge-sort primitive tracked in #10944:

- [ ] Coalesced global load/store staging around the blocked register layout used by the merge.

Each optimization should include correctness coverage and performance comparison against the baseline primitive across the supported group widths and partial-tile cases.

This issue can be closed once the techniques have been evaluated and the beneficial variants have been integrated or explicitly ruled out with supporting results.

### Describe alternatives you've considered

_No response_

### Additional context

_No response_

Start with the runtime-width group merge-sort primitive tracked in #10944. Evaluate coalesced global load/store staging around the blocked register layout, then compare correctness and performance with the baseline across supported group widths and partial-tile cases. Done means beneficial variants are integrated or explicitly ruled out with supporting results.

Written by the indexing model from the issue text.