[FEA]: Load-balance large segmented-sort segments across multiple thread blocks

### Is this a duplicate?

- [x] I confirmed there appear to be no [duplicate issues](https://github.com/NVIDIA/cccl/issues) for this request and that I agree to the [Code of Conduct](CODE_OF_CONDUCT.md)

### Area

CUB

### Is your feature request related to a problem? Please describe.

The current `DeviceSegmentedSort` large-segment path assigns an entire segment to one CTA. A very large segment can therefore occupy only one SM while the remaining SMs are idle.

This is particularly inefficient for workloads containing a small number of very large segments. Work should be decomposed by tiles so that multiple thread blocks can cooperate on the same segment.

It is a part of the segmented-sort building-block roadmap: (https://github.com/NVIDIA-dev/cccl_private/issues/829)

### Describe the solution you'd like

This issue can be closed once a tested segmented-sort large-segment path can schedule multiple thread blocks for one segment and demonstrates effective load balancing relative to the current implementation.

The implementation should include:

- Tests with a single segment requiring multiple thread blocks
- Tests with multiple differently sized large segments.
- Tests mixing empty, small, and large segments.
- Key-only and key-value tests.
- Ascending and descending tests.
- Restricted-bit-range tests.
- Validation that per-segment state and lookback do not cross segment boundaries.

cc: @colin-mcd

### Describe alternatives you've considered

_No response_

### Additional context

_No response_