NVIDIA / NVIDIA/TensorRT-Model-Connect
[Performance] qwen3-4b-instruct-2507 latency is 39.7% above reference
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- Dominant language
- Python
- Stars
- 254
- Forks
- 58
- Avg merge
- 1d 7h
- Merged PRs (30d)
- 235
Description
This was generated by AI during triage.
Summary
qwen3-4b-instruct-2507 completes aligned FP16 generation and matches exact token IDs, but TRTMC latency is 39.7% above the reference.
Observed behavior
- Precision: TRTMC FP16, reference FP16
- Output contract: exact token IDs (matched)
- Request: batch 1, 10 new tokens
- Measurement: 3 warmups followed by 10 iterations
- Candidate p50: 153.40 ms
- Reference p50: 109.81 ms
- Regression: +39.7% (allowed margin: 5%)
Expected behavior
The generation path should remain within the registered performance margin after warmup.
Acceptance criteria
- Profile prefill, decode, KV-cache access, and synchronization.
- Identify and fix the dominant bottleneck.
- Preserve exact-token output and the existing performance gate.
Reproduction platform
- Hardware: NVIDIA Thor X
- Architecture: aarch64
- TensorRT: 11.0
- GPU carveout: 48 GiB
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by profiling the generation path on NVIDIA Thor, separating prefill, decode, KV-cache access, and synchronization as described in the issue. Compare the candidate and reference measurements, then verify that the dominant bottleneck is addressed, exact token IDs remain unchanged, and latency returns within the 5% performance margin.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- python
- Domain
- machine-learning, performance
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100