NVIDIA / NVIDIA/AMGX

How is the bandwidth of non-symmetric matrices reduced for ILU(0) preconditioner

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Dominant language
Cuda
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Description

We have been experimenting with the GMRES solver with ILU(0) preconditioner. We would like to know how a non-symmetric matrix is re-ordered before computing the ILU(0) preconditioner? Could someone point to any documentation or sections of the code-base where this aspect can be understood?

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Research direction

Start with the GMRES solver and ILU(0) preconditioner references in the code base, then trace how non-symmetric matrices are reordered before ILU(0) is computed. Done means documenting the ordering and bandwidth behavior and pointing readers to the relevant code sections.

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Assessment

Domain
backend
Issue type
Documentation
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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