[ITensors] [ENHANCEMENT] Faster Computing Gradients of Variational Circuits with Hardware-Efficient Ansatz

I've developed an optimized version of apply specifically for variational circuits based on hardware-efficient ansatz. This approach leverages the one-qubit gates and non-parametrized entangling gates, offering a more efficient, albeit less general, solution. I'm interested in contributing this to the ITensors library and would like to gauge if there's interest in this addition.

In essence, I've written two separate functions:

1. An optimized apply version that does not computes the $\frac{\partial \text{apply}(\ket{\psi}, gates)}{\partial gates}$ pullback but only the $\frac{\partial \text{apply}(\ket{\psi}, gates)}{\partial \psi}$ pullback when dealing with non-parametrized gates.

2. A specialized apply version that computes the pullback for single-qubit gates more efficiently by taking advantage of their simpler structure. Note that as long as the gates input into apply are acting on different sites, we should be able to compute the pullback more efficiently. However, in this current implementation, only the single-qubit version has been developed.

These enhancements significantly reduced the computational cost of computing gradients in a system of $L=20$ with a depth of 6 and maxdim=60 from 290ms to approximately 180ms.

The issue does not name files, tests, or an entry point. Start by reviewing the existing apply implementation and how its pullbacks are defined, then compare the proposed non-parametrized and single-qubit variants against that behavior. Done means agreeing on scope and integrating validated gradient optimizations for the described hardware-efficient circuits.