Privileged IR: Add MSR register enums and implicit operands

### Problem Description

In #7916 we are adding support for the Intel CET extension. `OP_setssbsy` is a new instruction in this extension. While working on this instruction we found out that DynamoRIO's IR currently lacks support for modeling privileged MSRs and their associated implicit memory operands.

`OP_setssbsy`:
- **Semantics**: Reads the `IA32_PL0_SSP` MSR, performs an atomic 64-bit load and store to verify/set the busy bit in the supervisor shadow stack token at `[IA32_PL0_SSP]`, and updates `SSP`.
- **Current IR**: The decode table entry has no operands (`xx, xx, xx, xx, xx`), matching its 0-operand opcode (`F3 0F 01 E8`).
- **Gap**: Lacks register representation (`DR_REG_IA32_PL0_SSP` and `DR_REG_SSP`) and implicit memory load/store operands (`[IA32_PL0_SSP]`).

### Proposed Solution

Properly modeling these instructions in DynamoRIO requires some effort:

1. Add Privileged Register Enums (`DR_REG_IA32_PL0_SSP` and `DR_REG_SSP`).
2. Model `OP_setssbsy` with implicit MSR & memory operands:
- **Destinations**: `DR_REG_SSP`, implicit memory operand `[DR_REG_IA32_PL0_SSP]` (`OPSZ_8`).
- **Sources**: `DR_REG_IA32_PL0_SSP`, implicit memory operand `[DR_REG_IA32_PL0_SSP]` (`OPSZ_8`).
3. Go through existing privileged instructions and add their implicit MSR register operands.

Start at the decode table entry for OP_setssbsy and the existing privileged-instruction operand definitions. Inspect where register enums are declared, then model the listed MSR and implicit memory operands and review other privileged instructions for the same gap. Done means the new registers and implicit operands are represented consistently.

Written by the indexing model from the issue text.