Handle AArch64 non-address and privileged cache flush operations

This includes operations like `DC CSW` and others where the operand is not a memref, but an immediate denoting set-way. Currently, these are not handled by `instrument_memref` at all. We can probably put the address as 0 and some non-address-flush metadata too in the flush entry.

There's also `IC IALLU` and `IC IALLUIS` which invalidates all instruction cache. This also doesn't take any memory operand.

Start by tracing how AArch64 cache operations reach instrument_memref and how flush entries are represented. Review handling for DC CSW, other set-way operations, IC IALLU, and IC IALLUIS, then determine how non-address operations should be recorded with address 0 and non-address-flush metadata. Done means these operations are handled rather than omitted.

Written by the indexing model from the issue text.