DRCacheSim: Add config file for more complex TLB configs

Initially our TLB simulator only supports a simple 2-level hierarchy
with homogeneous L1 TLBs. To support more complex TLB layouts we
would want to add a configuration-file-based input to describe them.

We would want to support heterogeneous peers at any level, any number of
levels, and in fact perhaps any arbitrary tree. The only constraints
would be that I vs D splits must be at the lower levels.

We would need to add a tree data struct to the cache handling code.

The default would be our existing 2-level, with perhaps the parameters
matching the current underlying CPU.

The same is being done for caches and is being tracked in #1715.