drreg redundant re-load after app write

I observed this redundant load by drreg with drcachesim's -L0_filter
instrumentation:

rcx is reserved and written by the app, so drreg updates the saved value after an
app write to rcx, but doesn't have to re-load it as a src despite the next
app instr reading it (this happens 2x in a row here):

```
+112 L3 48 89 f1 mov %rsi -> %rcx
+115 m4 @0x000000004f6540b8 65 48 89 0c 25 98 00 mov %rcx -> %gs:0x00000098[8byte]
00 00
+124 m4 @0x000000004f6541a8 65 48 8b 0c 25 98 00 mov %gs:0x00000098[8byte] -> %rcx
00 00
+133 L3 48 29 c1 sub %rax %rcx -> %rcx
+136 m4 @0x000000004f654208 65 48 89 0c 25 98 00 mov %rcx -> %gs:0x00000098[8byte]
00 00
+145 m4 @0x000000004f654280 65 48 8b 0c 25 98 00 mov %gs:0x00000098[8byte] -> %rcx
00 00
+154 L3 48 83 f9 0f cmp %rcx $0x000000000000000f
```