ARM machine_cache_sync is not thread-safe

According to sections B2.6.5 (AArch64) and E2.6.5 (AArch32) of the ARM ARM, when one CPU writes instructions that will be executed by another CPU, a number of operations must be performed on the first CPU (these are implemented by machine_cache_sync), and the second CPU must execute an ISB instruction when the modified instructions are observable and before it executes them. There does not appear to be any mechanism in place to ensure that the second CPU executes an ISB.

I do not know how likely it is that this non-conformance to the architecture specification will cause problems in practice. It is perhaps very unlikely. Also, I cannot see any efficient and easy way of forcing an ISB onto every CPU/thread.