Add easier-to-use ARM SIMD alignment specification

I'm just going to paste the conversation about this here:

```
zhaoqin_, 2 questions on OP_vld1
1) split opcode or not for _lane and _dup
consider:
{OP_vld1_8 , 0xf420070f, "vld1.8" , VBq, xx, Mq, i2_4, xx, no, x, END_LIST},
{OP_vld1_8 , 0xf4a0000f, "vld1.8" , VBb_q, xx, Mb, i3_5, xx, no, x, END_LIST},
{OP_vld1_8 , 0xf4a00c0f, "vld1.8" , VBq, xx, Mb, xx, xx, no, x, END_LIST},
question, which is easier for you, which is easier for tool writter
technically we can distinguish if the person calling INSTR_CREATE_vld1 constructs a simd reg w/ a OPSZ_1_of_8 size
or we could have INSTR_CREATE_vld1_lane but not split opcode itself
or lack of immed could help distinguish the _dup case
in asm these are "{d0}", "{d0[2]}", "{d0[]}"
split would be the simplest way, right?
yes, split may be simplest
then sure
esp since the _16 case does have an immed for the _dup (but 2 immeds for _lane I guess)
2) the alignment is a multi-bit immed for plain and _lane forms
but for _dup they changed it: it's just 1 bit. 0 means align to just 1 (no alignment). 1 means align to element size.
should that be a 1-bit immed opnd?
or split the opcode
so OP_vld1_dup_align_16
and OP_vld1_dup_noalign_16 (better name?)
we can just have an alignment opnd
hmm actually the align values for the others are limited. in particular for _lane it is pretty much just element size or no align
just encoded as more bits, but only 2 combos are legal
ok, 1-bit immed opnd
no, I suggest to add a 1byte immed opnd
it could be used by both dup and lane
just for different instructions, we have different value range requirement
or something
you mean, instead of user having to pass 0 or 1 to dup and 16 or 32 to lane, they can pass 16 or 32 to dup and we convert it to 0 or 1?
should be 16 or 0 (or 32 or 0) depending on size
vs 1 or 0 for dup
how about a few enum value?
for the opnd
I will make a note, but it may be an extra feature we do much later (maybe I'll file an issue) and for now you have to know the encoding
```