pop (esp) has the wrong base for esp

_From [bruen...@google.com](https://code.google.com/u/109494838902877177630/) on April 03, 2014 09:39:18_

xref issue #164 xref https://code.google.com/p/drmemory/issues/detail?id=1502 Intel manual:
If the ESP register is used as a base register for addressing a destination
operand in memory, the POP instruction computes the effective address of
the operand after it increments the ESP register. For the case of a 16-bit
stack where ESP wraps to 0H as a result of the POP instruction, the
resulting location of the memory write is processor- family-specific.

But to solve this in DR we have to add a stack slot size to any existing
disp: it could be "pop 0x14(esp)" or sthg. We'd then have to decrement
the offset on encoding, and on disassembly to avoid confusion? For Intel
or AT&T modes, at least, as we do display the adjusted value for push:

0x50f34a35 51 push %ecx %esp -> %esp 0xfffffffc(%esp)[4byte]

_Original issue: http://code.google.com/p/dynamorio/issues/detail?id=1410_