DoubangoTelecom / DoubangoTelecom/compv
Align the data and stride on the cache line size if it's <128 and pow2(must be but who knows).
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- Dominant language
- C++
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- 212
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Description
This avoid two threads from accessing the same data from the same cache. If the data and stride are aligned on the cache line then, we're sure that we'll not have a lane crossing
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