Prototype alternative design for state circuit

The current version of the `StateCircuit` is implemented according to this [version](https://hackmd.io/@timofey/rJ3f6B0B3#Many-sub-tables-single-custom-gate) of the design, which splits each level of the Merkle tree into separate sets of columns thus making circuit wider. The constraints are implemented in custom gates per level of the tree. These gates have a low degree because relevant rows between levels are aligned via padding; thus extended domain (how many other rows gate accesses) is low.

The alternative design would rely on equality arguments instead of custom gates, allowing (but not necessarily) a single set of columns for all levels. The equality (aka permutation) argument is used for wiring two different cells together to enforce the equality of their values. All equality checks are added in the last phase of proof generation using rows/cells left after previous phases. It's tricky to predict the impact of permutation checks on overall performance as their added variably by proving the framework.

This task aims to prototype a permutation-based design for `StateCircuit` and compare it with the current implementation based on proof generation time and peak memory consumption. We don't care much about the proof size because it going to be verified in the aggregator circuit to reduce it in the very end.

## [Spec](https://hackmd.io/@timofey/rJ3f6B0B3)