Backseating-Committee-2k / Backseating-Committee-2k/vhdl
Divider fails timing.
Open
- Dominant language
- VHDL
- Stars
- 3
- Forks
- 0
- PR merge metrics
- No merged PRs in 30d
Description
The DIVMOD instruction uses the `/` and `mod` operators, which are combinatorial, and make the entire design fail timing.
Contributor guide
No contributing guide indexed for this repository
Research direction
Start by locating the DIVMOD instruction implementation and the timing reports or constraints used for the design. Investigate the `/` and `mod` operators there; done means the divider no longer causes the design to fail timing, although the issue does not specify a target or test.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100