Backseating-Committee-2k / Backseating-Committee-2k/vhdl
Connect data bus to memory
Open
- Dominant language
- VHDL
- Stars
- 3
- Forks
- 0
- PR merge metrics
- No merged PRs in 30d
Description
The data bus is currently connected to the textmode output only, which is sufficient for "Hello World", but not much else.
Contributor guide
No contributing guide indexed for this repository
Research direction
Start by locating the VHDL implementation of the data bus, the textmode output, and memory; the issue does not name specific files or tests. Trace how the bus currently reaches textmode and determine the intended memory connection. Done means the bus can access memory as well as textmode output, with behavior verified by the project's available checks.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 30/100