Backseating-Committee-2k / Backseating-Committee-2k/vhdl
CI for Synthesis
Open
- Dominant language
- VHDL
- Stars
- 3
- Forks
- 0
- PR merge metrics
- No merged PRs in 30d
Description
There is a self-hosted CI runner that has the FPGA toolchain available as a Docker image.
Find out how to use this, and implement CI for synthesis.
Contributor guide
No contributing guide indexed for this repository
Research direction
Start by investigating how the self-hosted CI runner exposes the FPGA toolchain Docker image. Determine the repository's existing CI entry points, then implement a synthesis CI job using that runner and image. Done means synthesis runs successfully in CI.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- docker
- Domain
- build-system, ci-cd
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 30/100