process-gap(spec-steward): ARCH-11 reverse-trace propagation has no machine check — same POL-006 finding class recurred in 5+ consecutive adversarial passes

## Summary

When a VP (verification property) gains a dual-anchor relationship (traces to more than one BC), the verification-coverage matrix (ARCH-11 in our project) must carry reverse-trace entries in ALL affected BC rows. The plugin has no machine check for this bidirectional consistency, and no agent owns it structurally. Result: the identical finding class recurred across five consecutive adversarial passes, each costing a full Lane-B dispatch + remediation burst + state-manager burst to fix ONE missing table row.

**Severity:** MEDIUM (process-gap — pure toil; every instance is machine-detectable)

## Evidence (ArcavenAE/switchboard-blue, vsdd-factory 1.0.0-rc.21, Phase 5)

Recurrence trail of the same POL-006/reverse-trace class across Lane-B passes:

- Pass 22: observation form
- Pass 24: F-P5P24-B-001 — ARCH-11 BC-2.02.001 row missing VP-042 reverse-trace (3 findings that pass)
- Pass 25: F-P5P25-B-001 — ARCH-11 BC-2.07.002 row missing VP-067 reverse-trace — sidecar explicitly notes "third consecutive instance of the same ARCH-11 reverse-trace pattern"
- Pass 26: two further instances

Our STATE.md carries it as a standing drift row (POL-006-DEFERRED-LINT): "Machine-checkable via ARCH-11↔VP-INDEX bidirectional lint. Burst 68b established clean baseline. Deferred to post-Phase-5 upstream issue filing." This issue is that filing.

## Root cause

- VP-INDEX rows carry `source_bc:` (forward trace). ARCH-11 rows carry per-BC VP lists (reverse trace). Nothing validates they are inverses of each other.
- spec-steward's governance checks (POL-001 changelog triangles, POL-002 row-sync) are prose-shape checks; there is no structural cross-artifact set-equality check.
- The adversary catches each instance eventually — but at the cost of a full fresh-context pass per missing row, which is the most expensive possible detector for a set-difference computation.

## Proposed fix

Ship a `traceability-lint` (skill or spec-steward step, run at every phase gate and before every adversarial dispatch):

1. Parse VP-INDEX: build map VP → {BCs} from `source_bc` frontmatter.
2. Parse the verification-coverage matrix: build map BC → {VPs} from table rows.
3. Assert the two are exact inverses; report any asymmetric pair as `POL-006-LINT: BC-X row missing VP-Y reverse-trace (VP-INDEX declares source_bc: BC-X)` and vice versa.
4. Wire into the orchestrator's gate checklist so a dirty lint blocks adversarial dispatch — the pass should never spend its perimeter on machine-checkable set differences.

Note this is the structural-validity kind of check (artifact well-formedness), not a health metric — it can gate without ceremony.

## Environment
- vsdd-factory 1.0.0-rc.21, project ArcavenAE/switchboard-blue (Go), Phase 5 CONVERGED after 39 passes