process-gap(consistency-validator+architect): architecture-graph edge vs integration-story constraint contradictions survive all spec gates

**Pattern: architecture-level spec permits a subsystem-to-subsystem edge; a later integration-level story forbids the same edge with stricter language; no gate detects the contradiction**

This session surfaced a direct contradiction between two specs that both live in `.factory/specs/`:

- `specs/architecture/dependency-graph.md` enumerates an edge `SS-A → SS-B (capability description)` as **permitted** (PULL pattern).
- `specs/stories/.../STORY-X.YY.INT-NN.md` Constraint #1 reads: "EventBus is the only integration channel: SS-B MUST emit `` via EventBus. A direct SS-B → SS-A reference is **FORBIDDEN** (autoload lifecycle hazard)." PUSH only.
- Constraint #7: "`` MUST NOT import `` directly."

Both specs were authored at different times; the integration story was written later with more context but the architecture graph was never updated to match. An implementer reading both chose the more permissive `dependency-graph.md` and shipped the PULL implementation. Adversary caught the contradiction on Pass-1 review.

### Why it survives existing gates

- **consistency-validator (#339)** scopes its checks to a file-type allowlist; integration-story constraints aren't cross-checked against architecture diagrams.
- **#131** covers URL/endpoint/path coherence — string-level, not architectural-edge-level.
- **#327** covers AC-trace anchors against BCs — vertical (story → BC), not horizontal (story → architecture spec).
- Phase-1d adversarial passes operate within file-type silos; cross-corpus architectural contracts have no dedicated lint.

### Mechanism

When an integration story (the `INT-*` family) declares a constraint on subsystem-to-subsystem coupling, that constraint should be reflected in:
- the dependency-graph edge listing (remove or annotate the direct edge),
- the BC for the cap (cite the integration-channel),
- the architect's ADR for the integration mechanism.

None of these are automatically synchronized. The integration story refines the architecture-level permission but does not invalidate it in the source spec.

### Suggested intervention

A spec-architectural-coherence lint that:
1. parses `dependency-graph.md` for edges (regex on `SS-NN → SS-MM` patterns),
2. parses all `STORY-*.INT-*.md` files for `MUST NOT import` / `FORBIDDEN` / `EventBus is the only channel` patterns over those edge endpoints,
3. flags any edge in the graph that is contradicted by an integration constraint, and fails CI / dispatch gate.

Could be plumbed into the consistency-validator (extending #339's scope to ADR/architecture/integration cross-corpus) or implemented as a new dedicated `architectural-contract-validator` agent.

### Provenance

Observed 2026-06-29 in a Phase-3 per-story adversarial Pass-1. Implementer made the reasonable call from the broader architecture graph; user adjudicated in favor of the stricter, later-authored integration constraint. Fix involved adding the EventBus signal + updating both specs. The contradiction had survived multiple Phase-1d convergence passes on the spec corpus.

(Product identifiers scrubbed per upstream-filing protocol.)