Azure / Azure/m

fp-hw-survey capture: x86-64 baseline (Intel + AMD)

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C++
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Description

Capture native FP behavior on **x86-64** (one Intel and one AMD part) with `crates/fp-hw-survey`. This anchors the **cross-architecture** divergence axis (x86-64 ↔ AArch64): `fmax`/`fmin` NaN handling, float→int saturation, flush-to-zero edges.

### Steps
```sh
cargo build --release -p fp-hw-survey
./target/release/fp-hw-survey info # confirm CPU brand + features (sse2/sse4.1/avx/fma/avx512f)
./target/release/fp-hw-survey selftest # must pass
./target/release/fp-hw-survey capture --label -
```

### What to attach to this issue
- The `info` output (CPU brand + detected features).
- The `selftest` result (must be clean — `capture` refuses to write otherwise).
- The **one-line NDJSON header** from the capture (durable provenance: cpu / os / features / date).
- The `capture-*.ndjson` file itself (attachment or link).

### Notes
- The x86-64 oracle covers the SSE-mappable subset only (arithmetic, `fmax`/`fmin`, `fsqrt`, `fma`, f32↔f64, truncating signed float→int, signed int→float); ops with no scalar SSE form are skipped. `MXCSR` status bits are translated into the AArch64 `FPSR` layout so flags compare directly across arches.
- **x86-64 self-test caveat:** the x86 asm was authored on an arm64 host; eyeball the first real-hardware `selftest` output before trusting the capture.

Part of the FP hardware survey fleet-capture campaign.

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