AntonioBerna / AntonioBerna/learn-verilog

Optimizations⚡

Open
#2 0 comments 0 reactions 1 assignee Claimed by @AntonioBerna View on GitHub
enhancement good first issue help wanted
Dominant language
Verilog
Stars
0
Forks
0
No merged PRs in 30d

Description

Optimize all code.

Contributor guide

No contributing guide indexed for this repository

Assessment

This issue has not been assessed yet.

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.