Possibly outdated Assembly code in STM32.GPIO#Lock_The_Pin

Greetings!

I was working on my project that uses STM32.GPIO package and faced a compilation error. Assembly code in STM32.GPIO#Lock_The_Pin works well for Cortex-M3 and up, but fails compilation on my Cortex-M0+. The comment in Lock_The_Pin justifies use of Assembly by the fact that setting pin's lock bit requires an exact write sequence, which is confirmed by the documentation:

RM0090 Rev 22
8.4.8 GPIO port configuration lock register (GPIOx_LCKR)
(x = A..I/J/K)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this write sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000
Access: 32-bit word only, read/write register

But isn't the write sequence guaranteed by the fact that GPIO_Peripheral is declared with Volatile? I understood it so that Volatile tells the compiler not to optimize and truly execute all reads and writes, in the order they are written in the source code. Is my reasoning correct or am i missing something? I am somewhat new to Ada and embedded and thus ignorant about many things.

Start at STM32.GPIO#Lock_The_Pin and inspect the Assembly sequence alongside the GPIO_Peripheral declaration. Compare the implementation with the cited RM0090 GPIOx_LCKR requirements and Cortex-M0+ compilation behavior; done means determining whether the current approach is valid or needs a documented, compilable change.