Page size restricted to <= 1/8th SRAM for v7-M MPU

Individual pages in the page heap are protected by subregions.
A page of size `2^N` must have its start address aligned to `2^N`.
However, for page sizes > 1/8th region size, the start address is
not guaranteed to be aligned to `2^N`.

Example: `2^N` = page size, `2^(N-1)` = 1/8th SRAM (32kB page size in a 128kB SRAM).

```
| |
+-----------+ <-- uvisor_config.page_end: 0x30000 = 3/8th * 128kB is aligned to 16kB.
| 32kB page |
+-----------+ <-- page start address: 0x30000 - 32kB = 0x10000 is not aligned to 32kB!!
| |
```

Due to these contradicting alignment requirements, it is not possible to have a page size larger than 1/8th region size.

This will be difficult to solve with the "1 page = 1 subregion" mapping, due to subregion alignment issues. Larger pages sizes will require a "1 page = `2^N` subregions" mapping. This enhancement can be added in the future without any impact on the user-facing API, except that larger page sizes will now be supported.

Start by tracing the page heap's page-to-subregion mapping and the alignment rules described in the issue. Verify the current 1-page-to-1-subregion behavior for pages larger than one-eighth of the SRAM region, then define the subregion mapping needed to support larger pages without changing the user-facing API.

Written by the indexing model from the issue text.