wrong clock phase in DP_SW.c

It looks like the template code has the clock out of phase.
https://github.com/ARMmbed/DAPLink/blob/master/source/daplink/cmsis-dap/SW_DP.c#L50

The spec says: "The target writes data to SWDIO on the rising edge of SWDCLK. The target reads data from SWDIO on the rising edge of SWDCLK."

SWD_READ_BIT should be reading the SWDIO line after setting SWCLK, not before. And since SWCLK idle state is low, SW_CLOCK_CYCLE should first set, then clear SWCLK. This is how Segger J-link does it.
https://interrupt.memfault.com/blog/img/debuggers/first_transaction.png

Read source/daplink/cmsis-dap/SW_DP.c around the referenced line, focusing on SWD_READ_BIT and SW_CLOCK_CYCLE. Compare their SWCLK and SWDIO ordering with the SWD specification quoted in the issue and the linked transaction image. Done means the clock phase and idle-low behavior match the stated rising-edge protocol.

Written by the indexing model from the issue text.