AEFeinstein / AEFeinstein/Super-2024-Swadge-FW
Documentation Request - Communications Pin and Mux Assignments
- Lingua principale
- C
- Stelle
- 34
- Fork
- 22
- Merge medio
- 3g 15h
- PR unite (30g)
- 10
Descrizione
I'm going through Pin Assignments for 2027 and am getting a little confused by the IO mapping we are using on Pulse.
Please confirm i'm reading these three right:
TX/RX on UART to the programming header - no other uses via IOmux.
USB(+/-) - Normal pins, no other uses via IOmux
JTAG pins (MTCK/MTDO/MTDI/MTMS) on GPIO39-42 are all repurposed for other GPIO via IOmux.
Onto Questions:
I2C - IOmux'd via GPIO41 and GPIO3, odd GPIO choice is there a specific reason?
Comms with the CH32 are via GPIO42 using a Single Wire IO. Can anyone confirm SWIO was chosen because it left us the most pins for the LED matrix? I'd like to have it on SPI or worst case I2C for the 2027 Swadge since it will be handling some button IO this year.
SAO Comms - I2C + GPIO40 & 42. Is there any Specific reason for 40 & 42?
And finally, the TFT is the one i'm having the most trouble deciphering. Seems to be on SPI3, with IOmux for GPIO to pull in the other signals. How integrated is the firmware with the SPI peripheral? We're only using a single SPI data line, out of curiosity does the screen support Dual or QSPI?
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