Expand P flag display into individual status bits (NV-BDIZC)

## Summary

The processor status register `P` (reported by VICE as `FL`) is currently shown as a raw hex byte. Expanding it into named flag bits makes it far easier to read CPU state at a glance during game debugging.

Bit layout (standard 6502, confirmed by vscode-kickass-studio `variablesHelper.ts`):

| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----|---|---|---|---|---|---|---|---|
| Flag | N | V | - | B | D | I | Z | C |
| Name | Negative | Overflow | (unused) | Break | Decimal | Interrupt disable | Zero | Carry |

---

## Implementation plan

### Option A — Enrich `_display` on the existing P register object (minimal)

In `commands.put_registers()` (`commands.py:230`), after building the `RegVal` for `P`, also set a richer `_display` string:

```python
if ghidra_name == 'P':
flags = 'NV-BDIZC'
bits = ''.join(f if (value >> (7-i)) & 1 else '.' for i, f in enumerate(flags))
display = f'P = {bits} (0x{value:02X})'
```

Result in the Registers panel: `P = N.-.DI.. (0x1A)`

No schema changes needed.

### Option B — Add child flag objects under the P register (richer, more effort)

Create child objects at paths like:
```
C64.Threads[0].Stack[0].Registers[P][N]
C64.Threads[0].Stack[0].Registers[P][Z]
...
```

Each would be a `Register` object with `value` set to the extracted bit. Requires:
1. A new schema type (or reuse `Register`) for single-bit children.
2. The `RegisterContainer` schema (`schema.xml:73-77`) would need an element that accepts nested children — currently it only allows `Register` elements, not nested containers.

**Recommendation**: start with Option A; add Option B only if Ghidra's register panel supports nested display well.

---

## Flag extraction snippet (for either option)

```python
FLAG_BITS = [
(7, 'N', 'Negative'),
(6, 'V', 'Overflow'),
(4, 'B', 'Break'),
(3, 'D', 'Decimal'),
(2, 'I', 'Interrupt'),
(1, 'Z', 'Zero'),
(0, 'C', 'Carry'),
]

def p_flag_display(value: int) -> str:
chars = list('NV-BDIZC')
bits = ''.join(c if (value >> (7-i)) & 1 else '.' for i, c in enumerate(chars))
return f'P = {bits} (0x{value:02X})'
```

---

## Files to change

- `src/main/py/src/vice/commands.py` — `put_registers()` (~line 241), add special-case for `ghidra_name == 'P'`
- `src/main/py/src/vice/schema.xml` — only if pursuing Option B